1. Field of the Invention
The present invention relates to a high-voltage MOS transistor comprising a semiconductor substrate, a gate electrode disposed on the semiconductor substrate with an insulation film interposed therebetween, a pair of first diffusion layers formed on a surface layer side of the semiconductor substrate and disposed apart from each other by a predetermined distance under the gate electrode, and a pair of second diffusion layers, each adjacent to the side of the respective first diffusion layers, facing away from the gate electrode, and having a dopant dose higher than that for the first diffusion layers, wherein a source region is made up of one of the first diffusion layers, and one of the second diffusion layers adjacent to the one of the first diffusion layers and a drain region is made up of the other of the first diffusion layers, and the other of the second diffusion layers, adjacent to the other of the first diffusion layers.
2. Description of the Related Art
As shown in FIG. 9, a common n-channel high-voltage MOS transistor 100 is provided with a gate electrode 106 made of polysilicon, disposed on a p-type silicon semiconductor substrate 102 with a gate insulation film 104 made up of a gate oxide film, interposed therebetween.
Lightly doped n-type diffusion layers 108, 110 are formed by implanting phosphorus ions in the order of 6.0 E 12 cm−2 at 70 keV by the ion implantation method using the gate electrode 106 as a mask. Heavily doped n-type diffusion layers 112, 114 are formed by implanting arsenic ions in the order of 1.0 E 15 cm−2 at 40 keV into regions away from the gate electrode 106, and inside the lightly doped n-type diffusion layers 108, 110, respectively. These are generally called n-type regions, one of which can form a source electrode 116, and the other of which can form a drain electrode 118.
With the n-channel high-voltage MOS transistor 100 described above, when the gate electrode 106 and source electrode 116 are in grounded condition, and a voltage at 20V is applied to the drain electrode 118, potential distribution will be as shown in FIG. 10(A).
More specifically, it is shown that a potential density is at the highest in a region of the lightly doped n-type diffusion layer 108, on the side of the drain electrode 118, and directly underneath the gate electrode 106, that is, in a boundary region between the gate electrode 106 and the drain electrode 118.
Accordingly, as shown in FIG. 10(B), electric field strength in the region is at the maximum inside the n-channel high-voltage MOS transistor 100. If the electric field strength when the transistor is in operation exceeds 1E 5V/cm, this will cause impact ionization, so that electrons and holes, having high energy, are injected in and arrested by the gate insulation film 104 disposed directly above, thereby inducing time-dependent changes in transistor characteristics such as Vt, Gm, Ids, and so on. More specifically, when the transistor is in operation, an impact ionization ratio will reach the maximum in the boundary region between the gate electrode 106 and the drain electrode 118, and the transistor characteristics are prone to time-dependent changes.
Particularly, with a high-voltage MOS transistor, since an operation voltage thereof (voltage applied in a state where the transistor is actually mounted in a device) is high for one thing, a high electric field tends to be developed in the boundary region. Accordingly, it can be said that the high-voltage MOS transistor is in an environment prone to time-dependent changes in the characteristics thereof as described above.
The time-dependent change of the characteristics is defined by a hot carrier lifetime. The hot carrier lifetime generally refers to time for the characteristic undergoing a change by 10%.
Accordingly, the higher a ratio of a time-dependent change of the characteristics (the more intense a time-dependent change is), the shorter the lifetime of hot carriers. That is, it means that an actual service life of a transistor is short. In other words, suppression of impact ionization is important from the viewpoint of reliability of the transistor.
In this connection, current generated due to impact ionization can be observed as substrate current. That is, the substrate current is proportional to an impact ionization ratio.
FIG. 11 shows a gate voltage—substrate current characteristic in a state where 20V is applied to the drain electrode 118 and the source electrode 116 is grounded, demonstrating that substrate current has a peak value in relation to gate voltage. It can be said that the impact ionization ratio is at its maximum in a voltage condition where the substrate current is at the maximum. In FIG. 11, the substrate current is at the maximum when the gate voltage is in a range of 3 to 4V.
Further, FIG. 12 shows a characteristic diagram, obtained by plotting relationship between maximum substrate current (Isub max) and a hot carrier lifetime (Ids) with a dopant dose of the lightly doped n-type diffusion layer 108 as a parameter.
It is evident from FIG. 12 that there is a strong co-relationship between the maximum substrate current (Isub max) and the hot carrier lifetime (Ids). Accordingly, the Isub max will become a key factor in evaluation of the hot carrier lifetime and the impact ionization ratio.
In the past, a process design has been made on the basis of the key factor described above such that the maximum substrate current (Isub max) becomes sufficiently small in order to obtain a hot carrier lifetime with satisfactory reliability (for example, 10 years).
FIG. 12 shows that the maximum substrate current (Isub max) per unit gate length needs to be not larger than 5 μA/μm in order to attain the hot carrier lifetime with the 10 year reliability.
Reduction in the maximum substrate current (Isub max) can be achieved by further lowering of dopant dose in the lightly doped n-type diffusion layer 108 as shown in FIG. 12, or by expansion of a gate length of the gate electrode 106, thereby rendering an electric field less intense.
With such methods as described, however, there has arisen a problem that the driving capacity of the transistor itself had to be inevitably sacrificed due to an increase in diffusion resistance of the source/drain, and channel resistance.